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Intel's new grid architecture: the data center of the "super highway"

One of the priorities of the data center architecture is to improve efficiency in order to achieve the best return on capital and maximize the output of the data center in limited space and electricity. The processor plays a fundamental role in data center optimization, and the choice of processor architecture has a significant impact on scalability and efficiency. To achieve the desired balance between these factors, you need vision, creativity and innovation, and these can not be achieved overnight.

Intel's extensive product portfolio embodies decades of experience in designing dedicated data center CPUs and platforms. Generation after generation, Intel continues to innovate core computing capabilities to improve processor performance. But our work did not stop there. All kernel connections and scalability improvements, fine tuning of memory hierarchies, and enhanced I / O are equally important, and these factors will ensure that the data center is primarily responsible for building the computational, network, and storage system scalability and efficiency.

Growing troubles: the challenges brought about by the scale

Add more kernel and connect it to ｃｒｅａｔｅ a multicore data center processor, which may sound simple, but the CPU kernel, memory hierarchy, and I / O subsystems provide a connection to these subsystems that require a careful architecture Critical Path. These interconnected, like a well-designed freeway, have the right number of lanes and ramps at key locations to allow traffic to flow all the way, rather than allowing people and goods to sit on the road and waste time.

Increase the number of processor cores and increase the memory and I / O bandwidth of each processor to meet the needs of a large number of data center loads - which constitute some of the challenges that must be addressed through creative architecture technologies. These challenges include:

Increase the bandwidth between memory, on-chip cache hierarchy, memory controller, and I / O controller. If the available interconnect bandwidth does not scale appropriately with other resources on the processor, the interconnect will be a bottleneck in limiting the efficiency of the system as frustrating traffic congestion.

Reduced access to delays from chip cache, main memory, or other kernel data. The access delay depends on the distance between the chip entities, the path to the request and the response, and the speed of the interworking operation. This is equivalent to the commuter time in the extended city vs compact city, the number of available paths, and the speed limit on the freeway.

Ｃｒｅａｔｅ energy-efficient ways to provide data from the chip cache and memory to the kernel and I / O. Because of the farther distance and higher bandwidth between each component, the energy required to complete the same task's data migration increases as more cores are added. Taking traffic as an example, as the city grows and commute distances increases, the time and energy wasted during commuting will make the available resources available for production work less.

Intel is committed to innovative architecture solutions that are ahead of the challenge when creating more powerful and efficient processors to meet the needs of existing and emerging workloads - such as artificial intelligence and deep learning. is focused on CPUvendor points for attention, Reliable quality Used CPUsuppliers, Server CPUvendor of the well-known brands, Professional supply Server CPUvendor and other projects. even though in the rapid development of the project ,Yue Yang Electronic always stressed the balance between external opportunities and internal management, attaches great importance to the core compet

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